1. Field of the Invention
This invention pertains in general to a method for manufacturing a semiconductor device and, more particularly, to a method for manufacturing trench capacitors.
2. Description of the Related Art
Trench capacitors have been developed as an alternative to planar and stacked capacitors in dynamic random access memory (DRAM) cells because trench capacitors provide comparatively large capacitance while occupying a comparatively small area on a semiconductor chip surface. Trench capacitors are characterized by deep and narrow trenches in the semiconductor substrate. An insulator formed on the trench walls serves as the capacitor dielectric. Capacitor plates are formed on either side of the insulator, and one of the plates is formed by refilling the trench with doped polysilicon. The capacitance (C) of a trench capacitor is determined as follows:   C  =            ε      ⁢              xe2x80x83            ⁢      A        d  
where ∈ is the permittivity of the capacitor dielectric, A is the capacitor area, and d is the thickness of the capacitor dielectric. From the foregoing relationship, the capacitance of a trench capacitor may be increased by forming a trench capacitor having a large area (A), or a thin capacitor dielectric (d).
One way to obtain a large capacitor area is to increase the depth of the trench capacitor. However, the circumference of the trench capacitor limits the depth of the trench that can be formed. In the manufacturing process of a trench capacitor, a mask that defines the circumference of the trench capacitor, is provided over the silicon wafer. An example of such a mask includes a combination of a silicon nitride (SixHy, wherein x and y are integers, e.g., Si3H4) layer and a borosilicate glass (BSG) layer. The mask is then patterned to remove portions of the mask to expose a defined silicon substrate region. This is followed with reactive ion etching (RIE) to form a trench. The BSG layer is removed during the RIE process. FIG. 1 shows a trench formed in a silicon substrate 2 with a remaining layer of silicon nitride 4 as a mask.
The trench is doped with impurities, such as arsenic, to make the trench sidewalls conductive, thereby forming one plate of a capacitor. A thin layer of sacrificial thermal oxide may be grown on the sidewalls to remove silicon damaged by the higher-energy ions used to etch the trench during the RIE process to provide smooth trench sidewalls. The optional thermal oxide layer may be removed with a diluted hydrogen fluoride (HF) solution. A layer of silicon nitride (SixHy) is deposited on the sidewalls using a chemical vapor deposition (CVD) process. The trench is then refilled with polysilicon doped with impurities such as phosphorus to form the other plate of the capacitor.
During the manufacturing of a DRAM product, however, a plurality of trench capacitors are formed. FIG. 2 shows the formation of a mask over silicon substrate 2 with a layer of silicon nitride 4 and a layer of BSG 6. FIG. 3 shows the forming of two trenches after the RIE process with the silicon nitride layer 4 and BSG layer 6 as a mask. BSG layer 6 is removed during the RIE process. Upon further processing according to the manufacturing process described above, these trenches will eventually become two trench capacitors.
As the density of DRAM products increases, the space between trench capacitors decreases. Furthermore, to achieve high capacitance, the trench capacitors are formed with increasing depths, which require longer etch time. However, bombardment by high-energy ions for an extended period of time during the RIE process may also remove portions of the silicon nitride layer, resulting in nitride faceting. This is shown in FIG. 4, which shows the removal of a portion of nitride layer 4A between two trenches. In situations involving excessive etching of the nitride layer in which a portion of the substrate between trenches is also removed, an electrical short is created between the neighboring trench capacitors when doped polysilicon is deposited to refill the trenches. To avoid an electrical short of neighboring trench capacitors, and minimize nitride faceting, the BSG layer generally has a thickness of at least 6500 xc3x85.
Accordingly, the present invention is directed to a method for manufacturing trench capacitors that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structures and methods particularly pointed out in the written description and claims thereof, as well as the appended drawings.
To achieve these and other advantages, and in accordance with the purpose of the invention as embodied and broadly described, there is provided a method for manufacturing a trench capacitor that includes forming a layer of silicon nitride over a silicon substrate, depositing a layer of borosilicate glass having a predetermined thickness over the layer of silicon nitride, patterning and defining the layer of borosilicate glass to expose two regions of the silicon substrate separated by a sacrificial mask, wherein the sacrificial mask includes the layer of borosilicate glass and the layer of silicon nitride, etching the two regions of the silicon substrate to form two trenches, each having sidewalls, and etching the sacrificial mask, wherein the predetermined thickness of the layer of borosilicate glass permits the sacrificial mask and a portion of the silicon substrate beneath the sacrificial mask to be removed, depositing a layer of silicon nitride on the sidewalls of the trenches, and depositing polysilicon into the trenches to form a single capacitor.
In one aspect of the invention, the step of depositing a layer of borosilicate glass having a predetermined thickness includes a step of depositing a layer of borosilicate glass having a thickness of approximately 6500 xc3x85.
Also in accordance with the present invention, there is provided a method for manufacturing a deep trench capacitor that includes defining a silicon substrate a surface, forming a layer of silicon nitride over the surface of the silicon substrate, depositing a layer of borosilicate glass having a predetermined thickness over the layer of silicon nitride, patterning and defining the layer of borosilicate glass to expose two regions of the surface of the silicon substrate separated by a sacrificial mask, wherein the sacrificial mask includes the layer of borosilicate glass and the layer of silicon nitride, the sacrificial mask has a higher etch rate than the remaining portions of the patterned and defined layers of silicon nitride and borosilicate glass, etching the two regions of the surface of the silicon substrate to form two trenches, wherein the two trenches are separated by a portion of silicon substrate having a height below the surface of the silicon substrate, depositing a layer of silicon nitride on the sidewalls of the trenches to form a dielectric layer, and depositing doped polysilicon into the trenches to form a single capacitor.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.